1. Field of the Invention
This invention relates to a semiconductor memory device, more specifically to a defective block management scheme of an EEPROM flash memory, in which electrically rewritable and non-volatile memory cells are used.
2. Description of the Related Art
A NAND-type flash memory has features as follows: the unit cell area is smaller than that of a NOR-type one; and it is easy to increase the capacitance. Recently, by use of a multi-level data storage scheme, in which one cell stores two or more bits, it has been developed a NAND-type flash memory with a further increased capacitance.
In the NAND-type flash memory with a binary data storage scheme, for example, an erase state with a negative threshold voltage is defined as data “1”; and a write state with a positive threshold voltage as data “0”.
The above-described principle of data bit assignment can be adapted to a four-level data storage scheme with respect to both of upper page and lower page. For example, four-level data “xy” (where “x” is an upper page; and “y” a lower page) can be defined as “11”, “10”, “01” and “00” in the order of cell threshold. In this scheme, both of the lower page read and the upper page read may be performed under the condition that a selected cell's on-state is defined as data “1” while an off-state is defined as data “0”.
By contrast, there is another four-level data storage scheme, in which “11”, “10”, “00” and “01” are assigned in the order of cell threshold voltage (for example, refer to JP-P2001-93288A). In this case, the lower page read in case of the upper page data “1” should be performed under the condition that a selected cell's off-state is read as “0” while the lower page read in case of the upper page data “0” should be performed under the condition that a selected cell's off-state is read as “1”.
A sense amplifier circuit always senses the off-state and on-state of a cell as data reversed in logic. Therefore, to distinguish between “0” read of the cell's off-state and “1” read of cell's on-state, it is required of an output circuit to be attached such a data inverting circuit that the lower page sense amplifier data is output outside the chip as it is when the upper page data is “1” while the lower page sense amplifier data is output together with level inverting when the upper page data is “0”.
On the other hand, there is known such a defective (or bad) block management method as follows. There is prepared a flag latch in a row decoder for selecting a block, in which a bad block flag is to be set, and it is controlled that no drive voltage is transferred to a block, in which the bad block flag is set. In this case, to make the external controller possible to judge whether the respective blocks are good or bad, it is prepared a bad block management area in one page, which is defined as a cell range where read/write is performed simultaneously. For example, the cell in the bad block management area is set to be normally-on with a read voltage applied (i.e., set to be in an erase state).
Setting the above-described bad block management area in the binary data storage scheme, the external memory controller may distinguish between a case of one page read data being all “0” in a normal block and another case of one page data being all “0” in a bad block because the bad block management area is “1” in the former case while it is “0” in the latter case.
However, in the four-level data storage scheme, in which read data may be inverted in the output circuit as described above, it often happens such a case that it is impossible to judge goodness/badness of a block if only monitoring the management area data. The reason is as follows: in case of the lower page read, in which data inverting is required, if all data “0” are inverted in the output circuit with respect to a bad block, the management area data becomes “1” (normal).